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Mahapatra, S., BharathKumar, P. and Alam, M.A. (2004) Investigation and Modeling of Interface and Bulk Trap Generation during Negative Bias Temperature Instability of P-MOSFETS. IEEE Transactions on Electron Devices, 51, 1371-1379.
https://doi.org/10.1109/ted.2004.833592

has been cited by the following article:

• TITLE: The Design of Ternary Field-Effect Transistors, DRAM Memory and NAND Flash Memory

  AUTHORS: Ben-Shan Wu, Xiang-Yao Wu, Sheng-Ji Xu

  KEYWORDS: Ternary, MOSFET Field-Effect Transistor, FinFET Field-Effect Transistor, Arithmetic Operations, Logical Operation, DRAM Memory, NAND Flash Memory

  JOURNAL NAME: World Journal of Engineering and Technology, Vol.13 No.2, May 27, 2025

  ABSTRACT: Based on the binary MOSFET and FinFET field-effect transistors, we have respectively designed ternary 0, +1, −1 digital signals using the improved MOSFET and FinFET field-effect transistors. On this basis, we have given the design principle and structure of ternary DRAM memory, that is, the reading +1, −1 and 0, and writing +1, −1 and 0 respectively, and also have given NAND flash memory, which include erasing operation, programming operation and reading operation. In addition, the arithmetic and logical operation rules of ternary are given. All the above works will lay a very important foundation for the development of ternary computer. All the above work will lay a very important foundation for the development of ternary computer.