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Rad, R.E., Kim, S.J., Hejazi, A., Ur Rehman, M.R., Bai, Z., Ziqi, D., et al. (2020) A Low Power 12-Bit Pipeline ADC with 40 MS/s Using a Modified OP-AMP. 2020 International Conference on Electronics, Information, and Communication (ICEIC), Barcelona, 19-22 January 2020, 1-3.
https://doi.org/10.1109/iceic49074.2020.9051373

has been cited by the following article:

• TITLE: Design of a 14-Bit 1 MS/s Successive Approximation Analog-to-Digital Converter

  AUTHORS: Qinghong Li, Xianguo Cao, Liangbin Wang, Mingjun Song

  KEYWORDS: Analog-to-Digital Converter, Capacitor Mismatch, Calibration, Successive Approximation

  JOURNAL NAME: Journal of Power and Energy Engineering, Vol.12 No.11, November 26, 2024

  ABSTRACT: A 14-bit successive approximation analog-to-digital converter (SAR ADC) with capacitive calibration has been designed based on the SMIC. 18 μm CMOS process. The overall architecture is in fully differential form to eliminate the effect caused by common mode noise. Meanwhile, the digital-to-analog converter (DAC) is a two-stage structure, which can greatly reduce the area of the capacitor array compared with the traditional DAC structure. The capacitance calibration module is mainly divided into the mismatch voltage acquisition phase and the calibration code backfill phase, which effectively reduces the impact of the DAC mismatch on the accuracy of the SAR ADC. The design of this paper is based on cadence platform simulation verification, simulation results show that when the sampling rate is 1 MS/s, the power supply voltage is 5 V and the reference voltage is 4.096 V, the effective number of bits (ENOB) of the ADC is 13.49 bit, and the signal-to-noise ratio (SNR) is 83.3 dB.