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F. Esfahani, P. Basedau, R. Ryter and R. Becker, “A Fourth Order Continuous-Time Complex Sigma-Delta ADC for Low-IF GSM and EDGE Receivers, in VLSI Circuits,” Symposium on Digest of Technical Papers, 12-14 June 2003, pp. 75-78.

has been cited by the following article:

• TITLE: A New Approach to Complex Bandpass Sigma Delta Modulator Design for GPS/Galileo Receiver

  AUTHORS: Nima Ahmadpoor, Ebrahim Farshidi

  KEYWORDS: Continuous Time; Quadrature; Sigma Delta; MOS; Modulator; OTA

  JOURNAL NAME: Circuits and Systems, Vol.3 No.1, December 31, 2011

  ABSTRACT: In this paper, new complex band pass filter architecture for continuous time complex band pass sigma delta modulator is presented. In continuation of paper the modulator is designed for GPS and Galileo receiver. This modulator was simulated in standard 0.18 μm CMOS TSMC technology and has bandwidth of 2MHz and 4MHz for GPS and Galileo centered in 4.092 MHz. The dynamic range (DR) is 56.5/49 dB (GPS/Galileo) at sampling rate of 125 MHz. The modulator has power consumption of 4.1 mw with 3 V supply voltage.