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T. Anantharaman and B. Bisiani, “A Hardware Accelerator for Speech Recognition Algorithms,” Proceedings of the 13th Annual International Symposium on Computer Architecture, Vol. 14, No. 2, 1986, pp. 216-223.

has been cited by the following article:

• TITLE: A C-Based Variable Length and Vector Pipeline Architecture Design Methodology and Its Application

  AUTHORS: Takashi Kambe, Nobuyuki Araki

  KEYWORDS: Variable Length and Vector Pipeline Architecture; C-Based Design; System LSI; Speech Recognition

  JOURNAL NAME: Circuits and Systems, Vol.3 No.1, December 31, 2011

  ABSTRACT: The size and performance of a System LSI depend heavily on the architecture which is chosen. As a result, the architecture design phase is one of the most important steps in the System LSI development process and is critical to the commercial success of a device. In this paper, we propose a C-based variable length and vector pipeline (VVP) architecture design methodology and apply it to the design of the output probability computation circuit for a speech recognition system. VVP processing accelerated by loop optimization, memory access methods, and application-specific cir- cuit design was implemented to calculate the Hidden Markov Model (HMM) output probability at high speed and its performance is evaluated. It is shown that designers can explore a wide range of design choices and generate complex circuits in a short time by using a C-based pipeline architecture design method.