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E. Casseau and B. Le Gal, “High-Level Synthesis for the Design of FPGA-Based Signal Processing Systems,” International Symposium on Systems, Architectures, Modeling, and Simulation, SAMOS’09, 20-23 July 2009, pp. 25-32.

has been cited by the following article:

• TITLE: System-on-Chip Design Using High-Level Synthesis Tools

  AUTHORS: Erdal Oruklu, Richard Hanley, Semih Aslan, Christophe Desmouliers, Fernando M. Vallina, Jafar Saniie

  KEYWORDS: System Level Design; High Level Synthesis; Field Programmable Gate Arrays; Fourier Transform

  JOURNAL NAME: Circuits and Systems, Vol.3 No.1, December 31, 2011

  ABSTRACT: This paper addresses the challenges of System-on-Chip designs using High-Level Synthesis (HLS). HLS tools convert algorithms designed in C into hardware modules. This approach is a practical choice for developing complex applications. Nevertheless, certain hardware considerations are required when writing C applications for HLS tools. Hence, in order to demonstrate the fundamental hardware design concepts, a case studyis presented. Fast Fourier Transform (FFT) implementation in ANSI C is examined in order to explore the important design issues such as concurrency, data recurrences and memory accesses that need to be resolved before generating the hardware using HLS tools. There are additional language constraints that need to be addressed including use of pointers, recursion and floating point types.