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Manjith, B.C. (2019) Improving Overall Parallelism in AES Accelerator Using BRAM and Multiple Input Blocks. 2019 Innovations in Power and Advanced Computing Technologies (i-PACT), Vellore, 22-23 March 2019, 1-5.
https://doi.org/10.1109/i-PACT44901.2019.8960016

has been cited by the following article:

• TITLE: A High Efficiency Hardware Implementation of S-Boxes Based on Composite Field for Advanced Encryption Standard

  AUTHORS: Yawen Wang, Sini Bin, Shikai Zhu, Xiaoting Hu

  KEYWORDS: Advanced Encryption Standard (AES), S-Box, Tower Field, Hardware Implementation, Application Specific Integration Circuit (ASIC)

  JOURNAL NAME: Journal of Computer and Communications, Vol.12 No.4, April 30, 2024

  ABSTRACT: The SubBytes (S-box) transformation is the most crucial operation in the AES algorithm, significantly impacting the implementation performance of AES chips. To design a high-performance S-box, a segmented optimization implementation of the S-box is proposed based on the composite field inverse operation in this paper. This proposed S-box implementation is modeled using Verilog language and synthesized using Design Complier software under the premise of ensuring the correctness of the simulation result. The synthesis results show that, compared to several current S-box implementation schemes, the proposed implementation of the S-box significantly reduces the area overhead and critical path delay, then gets higher hardware efficiency. This provides strong support for realizing efficient and compact S-box ASIC designs.