Article citationsMore>>

Kumar, T. M., Reddy, K. S., Rinaldi, S., Parameshachari, B. D., & Arunachalam, K. (2021). A Low Area High Speed FPGA Implementation of AES Architecture for Cryptography Application. Electronics, 10, Article No. 2023.
https://doi.org/10.3390/electronics10162023

has been cited by the following article:

SCIRP Newsletter
Copyright © 2006-2026 Scientific Research Publishing Inc. All Rights Reserved.
Top