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Musalgaonkar, G., Sahay, S., Saxena, R.S. and Kumar, M.J. (2019) A Line Tunneling Field-Effect Transistor Based on Misaligned Core—Shell Gate Architecture in Emerging Nanotube FETs. IEEE Transactions on Electron Devices, 66, 2809-2816.
https://doi.org/10.1109/TED.2019.2910156

has been cited by the following article:

• TITLE: Simulation Study of Nanoscale FDSOI MOSFET Characteristics

  AUTHORS: Towhid Adnan Chowdhury

  KEYWORDS: Fully Depleted, Silicon on Insulator, Threshold Voltage, Subthreshold Slope, Leakage Current, Gate Length

  JOURNAL NAME: Soft Nanoscience Letters, Vol.13 No.3, July 19, 2023

  ABSTRACT: Silicon on insulator (SOI) technology permits a good solution to the miniaturization as the MOSFET size scales down. This paper is about to compare the electrical performance of nanoscale FD-SOI MOSFET at various gate lengths. The performance is compared and contrasted with the help of threshold voltage, subthreshold slope, on-state current and leakage current. Interestingly, by decreasing the gate length, the leakage current and on-state current are increased but the threshold voltage is decreased and the sub-threshold slope is degraded. Silvaco two-dimensional simulations are used to analyze the performance of the proposed structures.