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Ijjada, S.R., Ayyanna, G., Reddy, G.S. and Rao, D.V.M. (2011) Performance of Different CMOS Logic Styles for Low Power and High Speed. International Journal of VLSI Design & Communication Systems (VLSICS), 2, No. 2.

has been cited by the following article:

• TITLE: NP-Domino, Ultra-Low-Voltage, High-Speed, Dual-Rail, CMOS NOR Gates

  AUTHORS: Ali Dadashi, Omid Mirmotahari, Yngvar Berg

  KEYWORDS: Ultra Low Voltage (ULV), Semi-Floating-Gate (SFG), Speed, NOR Gate, Monte Carlo, TSMC 90 nm, CMOS

  JOURNAL NAME: Circuits and Systems, Vol.7 No.8, June 27, 2016

  ABSTRACT: In this paper, novel ultra low voltage (ULV) dual-rail NOR gates are presented which use the semi-floating-gate (SFG) structure to speed up the logic circuit. Higher speed in the lower supply voltages and robustness against the input signal delay variations are the main advantages of the proposed gates in comparison to the previously reported domino dual-rail NOR gates. The simulation results in a typical TSMC 90 nm CMOS technology show that the proposed NOR gate is more than 20 times faster than conventional dual-rail NOR gate.