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Gharsalli, F., Meftali, S., Rousseau, F. and Jerraya, A. (2002) Automatic Generation of Embedded Memory Wrapper for Multiprocessor SoC. Proceedings 2002 Design Automation Conference (IEEE Cat. No.02CH37324), New Orleans, LA, 10-14 June 2002, 596-601. https://doi.org/10.1109/DAC.2002.1012695

has been cited by the following article:

• TITLE: Multi-Memory Grouping Wrapper with Top Level BIST Algorithm

  AUTHORS: Narek Mamikonyan, Suren Abazyan, Vakhtang Janpoladov

  KEYWORDS: BIST, Memory Wrapper, Memory Bit

  JOURNAL NAME: Open Access Library Journal, Vol.7 No.5, April 24, 2020

  ABSTRACT: This algorithm integrates second level Built in self-test (BIST) into multiple memory grouping wrapper. Second level BIST brings additional reliability into the memory system while fastening testing time. Main approach is to test whole memory modules from top level by numerous step count of which can be modified based on power consumption requirement and overheat conditions. The worst case of the algorithm can be observed by the time when the number of steps is equal to the number of memory modules, otherwise the testing time will be relative to 1/N (N is the number of steps). The main advantage of memory wrapping methodology is the possibility of increasing variety of the number of bits and the number of cells in the memory, while using limited memories provided by foundry.