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Liu, D.-S., Zou, X.C., Zhang, F., et al. (2006) Embeded EEPROM Memory Achieving Lower Power-New Design of EEPROM Memory for RFID Tag IC. IEEE Circuits and Devices Magazine, 22, 53-59.
https://doi.org/10.1109/MCD.2006.307277

has been cited by the following article:

• TITLE: Model Design of Electrically Erasable EEPROM Memory Cell

  AUTHORS: Lei Zhao

  KEYWORDS: EEPROM Memory, Circuit Design, Circuit Simulation

  JOURNAL NAME: Journal of Computer and Communications, Vol.8 No.4, April 23, 2020

  ABSTRACT: This article introduces an EEPROM memory cell model that is different from the equivalent capacitance model. This model uses high-frequency components in circuit design, including MOS transistors, zener diodes, resistors, capacitors, etc., and builds a model that can be used in most analog environments. The simulation of the transient process of write and read operations helps designers understand the working principle of EEPROM, and it can also be applied to the overall circuit design. According to the structure and working principle of the EEPROM cell device, a model of its equivalent circuit is established, and the read, write, and erase operations of the EEPROM cell are transiently simulated using this model. The simulation results verify the correctness of the model.