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Chan, T., Cong, J., Kong, T. and Shinnerl, J. (2000) Multilevel Optimization for Large-Scale Circuit Placement. IEEE/ACM International Conference on Computer-Aided Design, San Jose, CA, 5-9 November 2000, 171-176.

has been cited by the following article:

• TITLE: Standard Cell Placement Optimization Using Quadratic Placement Algorithm

  AUTHORS: Suren Abazyan, Narek Mamikonyan, Vakhtang Janpoladov

  KEYWORDS: Placement, Optimization, Physical Design, Quadratic Placement

  JOURNAL NAME: Open Access Library Journal, Vol.7 No.4, April 8, 2020

  ABSTRACT: Designs including tens of millions of standard cells in one chip are commonly used in current IC projects, so finding optimal location on a chip surface for each logic cell is a very important step in IC design. Apart from finding room for logic cell placement with minimum chip area, length of connecting wires is also playing big role and needs to be taken under control. In this paper, research and implementation of standard cell placement-optimizations’ quadratic algorithm is described. Main research is on runtime and wire length. For 5K standard cells, algorithm implementation takes 83 second.