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Y. Cao, P. Leroux, W. De Cock and M. Steyaert, “A 1.7mW 11b 1-1-1-MASH Δ-Σ Time-to-Digital Converter,” 2011 IEEE International Solid State Circuits Conference, San Francisco, 20-24 February 2011, pp. 480-482. doi:10.1109/ISSCC.2011.5746406

has been cited by the following article:

• TITLE: Single-Stage Vernier Time-to-Digital Converter with Sub-Gate Delay Time Resolution

  AUTHORS: Chin-Hsin Lin, Marek Syrzycki

  KEYWORDS: Vernier Time-to-Digital Converter, Dynamic-Logic Phase Frequency Detector

  JOURNAL NAME: Circuits and Systems, Vol.2 No.4, October 17, 2011

  ABSTRACT: This paperpresents a single-stage Vernier Time-to-Digital Converter (VTDC) that utilizes the dynamic-logic phase detector. The zero dead-zone characteristic of this phase detector allows for the single-stage VTDC to deliver sub-gate delay time resolution. The single-stage VTDC has been designed in 0.13μm CMOS technology. The simulation results demonstrate a linear input-output characteristic for input dynamic range from 0 to 1.6ns with a time resolution of 25ps.