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M. Sinangil, V. Naveen and A. P. Chandrakasan, “A Reconfi-gurable 8T Ultra–Dynamic Voltage Scalable (U-DVS) SRAM in 65nm CMOS,” IEEE Journal Solid-State of Circuits, Vol. 44, No. 11, 2009, pp. 3163-3173. doi:10.1109/JSSC.2009.2032493

has been cited by the following article:

• TITLE: Stability and Leakage Analysis of a Novel PP Based 9T SRAM Cell Using N Curve at Deep Submicron Technology for Multimedia Applications

  AUTHORS: Shilpi Birla, Rakesh Kumar Singh, Manisha Pattanaik

  KEYWORDS: N Curve, Scaling, SVNM (Static Voltage Noise Margin), Leakage Power, 9T SRAM Cell

  JOURNAL NAME: Circuits and Systems, Vol.2 No.4, October 17, 2011

  ABSTRACT: Due to continuous scaling of CMOS, stability is a prime concerned for CMOS SRAM memory cells. As scaling will increase the packing density but at the same time it is affecting the stability which leads to write failures and read disturbs of the conventional 6T SRAM cell. To increase the stability of the cell various SRAM cell topologies has been introduced, 8T SRAM is one of them but it has its limitation like read disturbance. In this paper we have analyzed a novel PP based 9T SRAM at 45 nm technology. Cell which has 33% increased SVNM (Static Voltage Noise Margin) from 6T and also 22%.reduced leakage power. N curve analysis has been done to find the various stability factors. As compared to the 10T SRAM cell it is more area efficient.