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Sun, Y. and Cavallaro, J.R. (2013) VLSI Architecture for Layered Decoding of QC-LDPC Codes With High Circulant Weight. IEEE Transactions on Very Large Scale Integration (VLSI) Systems, 21, 1960-1964. https://doi.org/10.1109/TVLSI.2012.2220388

has been cited by the following article:

• TITLE: A Highly Compatible Circular-Shifting Network for Partially Parallel QC-LDPC Decoder

  AUTHORS: Yanzhi Wang, Zhenzhi Wu, Peipei Liu, Ning Guan, Hua Wang

  KEYWORDS: Partially Parallel Layered Decoding, Circular-Shifting Network, QC-LDPC Decoder, Arbitrary Expansion Factor

  JOURNAL NAME: International Journal of Communications, Network and System Sciences, Vol.10 No.5B, May 26, 2017

  ABSTRACT: The conventional methodology for designing QC-LDPC decoders is applied for fixed configurations used in wireless communication standards, and the supported largest expansion factor Z (the parallelism of the layered decoding) is a fixed number. In this paper, we study the circular-shifting network for decoding LDPC codes with arbitrary Z factor, especially for decoding large Z (Z P) codes, where P is the decoder parallelism. By buffering the P-length slices from the memory, and assembling the shifted slices in a fixed routine, the P-parallelism shift network can process Z-parallelism circular-shifting tasks. The implementation results show that the proposed network for arbitrary sized data shifting consumes only one times of additional resource cost compared to the traditional solution for only maximum P sized data shifting, and achieves significant saving on area and routing complexity.