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Narendra, S., De, V., Borkar, S., Antoniadis, D. and Chandrakasan, A. (2002) Full-Chip Sub-Threshold Leakage Power Prediction Model for Sub-0.18 um CMOS. International Symposium on Low Power Electronincs and Design, Monterey, CA, 12-14 August 2002, 19-23.
https://doi.org/10.1145/566408.566415

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