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Kim, K., Yu, W. and Cho, S. (2014) A 9 Bit, 1.12 ps Resolution 2.5 b/Stage Pipelined Time-to-Digital Converter in 65 nm CMOS Using Time-Register. IEEE Journal of Solid-State Circuits, 49, 1007-1016.
https://doi.org/10.1109/JSSC.2013.2297412

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