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M. Abo and P. R. Gray, “A 1.5 V, 10-bit, 14 MS/s CMOS pipeline analog-to-digital converter,” IEEE Journal Solid- State Circuits, Vol. 34, No. 5, pp. 599–606, May 1999.

has been cited by the following article:

• TITLE: A Simple On-Chip Automatic Tuning Circuit for Continuous-Time Filter

  AUTHORS: Chia-Hsiung KAO, Ping-Yu TSAI, I-Fan CHANG

  KEYWORDS: Automatic, Tuning, Voltage-Controlled Filter (VCF), Single-Time Constant (STC)

  JOURNAL NAME: International Journal of Communications, Network and System Sciences, Vol.3 No.1, January 20, 2010

  ABSTRACT: A simple on-chip automatic frequency tuning circuit is proposed. The tuning circuit is modified from voltage-controlled filter (VCF) frequency tuning circuit. We utilize an operational transconductance amplifier and a capacitor to from a single-time constant (STC) circuit which can produce a controllable delay time clock to tune the frequency of the filter. It can efficiently reduce the deviations in the 3 dB bandwidth from the variations of PVT (Process, Voltage and Temperature). The design of the STC circuit is simpler than VCF and it has less chip area. The chip has been implanted using TCMC 0.35 μm CMOS technology and the power consumption is less than 9.05 mW.