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Gupta, R., Tutuianu, B. and Pileggi, L.T. (1997) The Elmore Delay as a Bound for RC Trees with Generalized Input Signals. IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems, 16, 95-104.
https://doi.org/10.1109/43.559334

has been cited by the following article:

• TITLE: Study of Timing Characteristics of NOT Gate Transistor Level Circuit Implemented Using Nano-MOSFET by Analyzing Sub-Band Potential Energy Profile and Current-Voltage Characteristic of Quasi-Ballistic Transport

  AUTHORS: Chek Yee Ooi, Soo King Lim

  KEYWORDS: Theoretical, Simulation, Nano-MOSFET, Transistor Level, Quasi-Ballistic

  JOURNAL NAME: World Journal of Nano Science and Engineering, Vol.6 No.4, December 29, 2016

  ABSTRACT: This paper presents the quasi-ballistic electron transport of a symmetric double-gate (DG) nano-MOSFET with 10 nm gate length and implementation of logical NOT transistor circuit using this nano-MOSFET. Theoretical calculation and simulation using NanoMOS have been done to obtain parameters such as ballistic efficiency, backscattering mean free path, backscattering coefficient, critical length, thermal velocity, capacitances, resistance and drain current. NanoMOS is an on-line device simulator. Theoretical and simulated drain current per micro of width is closely matched. Transistor loaded NOT gate is simulated using WinSpice. Theoretical and simulated value of rise time, fall time, propagation delay and maximum signal frequency of logical NOT transistor level circuit is closely matched. Quasi-ballistic transport has been investigated in this paper since modern MOSFET devices operate between the drift-diffusion and ballistic regimes. This paper aims to enable modern semiconductor device engineers to become familiar with both approaches.