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Loke, A., Wu, Z.-Y., Moallemi, R., Cabler, D., Lackey, C., Wee, T.T. and Doyle, B. (2010) Constant-Current Threshold Voltage Extraction in HSPICE for Nanoscale CMOS Analog Design. Synopsys Users Group (SNUG), San Jose, Advanced Micro Devices, Inc.

has been cited by the following article:

• TITLE: Comparative Methodical Assessment of Established MOSFET Threshold Voltage Extraction Methods at 10-nm Technology Node

  AUTHORS: Yashu Swami, Sanjeev Rai

  KEYWORDS: Threshold Voltage, Constant Current Source Technique, Linear Extrapolation Technique, Threshold Voltage Estimation Techniques, Short Channel Effects, Drift Diffusion Model, Resistive Load Inverter, Noise Margin Analysis

  JOURNAL NAME: Circuits and Systems, Vol.7 No.13, November 30, 2016

  ABSTRACT: Threshold voltage (VTH) is the most evocative aspect of MOSFET operation. It is the crucial device constraint to model on-off transition characteristics. Precise VTH value of the device is extracted and evaluated by several estimation techniques. However, these assessed values of VTH diverge from the exact values due to various short channel effects (SCEs) and non-idealities present in the device. Numerous prevalent VTH extraction methods are discussed. All the results are verified by extensive 2-D TCAD simulation and confirmed through analytical results at 10-nm technology node. Aim of this research paper is to explore and present a comparative study of largely applied threshold extraction methods for bulk driven nano-MOSFETs especially at 10-nm technology node along with various sub 45-nm technology nodes. Application of the threshold extraction methods to implement noise analysis is briefly presented to infer the most appropriate extraction method at nanometer technology nodes.