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Wentzlaff, D., Griffin, P., Hoffmann, H., Bao, L., Edwards, B., Ramey, C., Mattina, M., Miao, C.-C., Brown III, J.F. and Agarwal, A. (2007) On-Chip Interconnection Architecture of the Tile Processor. IEEE Micro, 27, 15-31.
http://dx.doi.org/10.1109/MM.2007.4378780

has been cited by the following article:

• TITLE: Twist-Routing Algorithm for Faulty Network-on-Chips

  AUTHORS: Kunwei Zhang, Thomas Moscibroda

  KEYWORDS: Network-on-Chip (NoC), Fault-Tolerant Routing, Maze-Routing Algorithm, GOAFR+ Algorithm, Bounding Circle

  JOURNAL NAME: Journal of Computer and Communications, Vol.4 No.14, November 11, 2016

  ABSTRACT: This paper introduces Twist-routing, a new routing algorithm for faulty on-chip networks, which improves Maze-routing, a face-routing based algorithm which uses deflections in routing, and archives full fault coverage and fast packet delivery. To build Twist-routing algorithm, we use bounding circles, which borrows the idea from GOAFR+ routing algorithm for ad-hoc wireless networks. Unlike Maze-routing, whose path length is unbounded even when the optimal path length is fixed, in Twist-routing, the path length is bounded by the cube of the optimal path length. Our evaluations show that Twist-routing algorithm delivers packets up to 35% faster than Maze-routing with a uniform traffic and Erdos-Rényi failure model, when the failure rate and the injection rate vary.