TITLE:
High-Performance FIR Filter Implementation Using Anurupye Vedic Multiplier
AUTHORS:
S. Jayakumar, Dr. A. Sumathi
KEYWORDS:
Finite Impulse Response (FIR) Filter, Urdhava Triyagbhyam, Anurupye Vedic Multiplier, Very High-Speed Hardware Description Language (VHDL)
JOURNAL NAME:
Circuits and Systems,
Vol.7 No.11,
September
16,
2016
ABSTRACT: In
this, today’s world immeasurable analysis goes within the field of communication and
signal processing applications. The FIR filter is mostly employed in filtering
applications to enhance the quality of the signal. In any processor, the
performance of the system is based on the speed of the multiplier unit involved
in its operation. Since multiplier forms the indispensable building blocks of
the FIR filter system. Its performance has contributed in determining the
execution of the FIR filter system. Also, due to the tremendous development in
the technology, many approaches such as an array, Vedic methods are made to speed up the
multiplier computations. The problem in speed-up
operation and resource utilization of hardware with all the conventional
methods due to the critical path found in partial products has to be optimized
using proposed method. This paper presents the implementation and execution of
a FIR Filter design using Anurupye multiplier. Here the FIR filter is examined
by using various multiplier algorithms such as Anurupye, Urdhava Tiryagbhyam,
and array multipliers. The FIR filter is simulated for analyzing delay; area
and power are meted out and lessened by utilizing proposed Anurupye multiplier. The FIR
filter design utilizing proposed multiplier offers delay around 18.99 and only
4% of LUT slice utilization compared to existing methods. This architecture is
coded in VHDL, simulated using the ModelSim and synthesized with
Xilinx.