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Naseer, R., Boulghassoul, Y., Draper, J., DasGupta, S. and Witulski, A. (2007) Critical Charge Characterization for Soft Error Rate Modeling in 90nm SRAM. Proceeding of IEEE International Symposium on Circuits and Systems (ISCAS), New Orleans, 27-30 May 2007, 1879-1882.

has been cited by the following article:

• TITLE: Error Correction Circuit for Single-Event Hardening of Delay Locked Loops

  AUTHORS: S. Balaji, S. Ramasamy

  KEYWORDS: Delay-Locked Loop, Single Event Transients, Error Correction Circuit

  JOURNAL NAME: Circuits and Systems, Vol.7 No.9, July 20, 2016

  ABSTRACT: In scaled CMOS processes, the single-event effects generate missing output pulses in Delay-Locked Loop (DLL). Due to its effective sequence detection of the missing pulses in the proposed Error Correction Circuit (ECC) and its portability to be applied to any DLL type, the ECC mitigates the impact of single-event effects and completes its operation with less design complexity without any concern about losing the information. The ECC has been implemented in 180 nm CMOS process and measured the accuracy of mitigation on simulations at LETs up to 100 MeV-cm2/mg. The robustness and portability of the mitigation technique are validated through the results obtained by implementing proposed ECC in XilinxArtix 7 FPGA.