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Worley, E.R., Gupta, R., Jones, B., Kjar, R., Nguyen, C. and Tennyson, M. (1995) Sub-Micron Chip ESD Protection Schemes Which Avoid Avalanching Junctions. Electrical Overstress/Electrostatic Discharge Symposium Proceedings, Phoenix, 12-14 September 1995, 13-20.
http://dx.doi.org/10.1109/eosesd.1995.478263

has been cited by the following article:

• TITLE: On a Parasitic Bipolar Transistor Action in a Diode ESD Protection Device

  AUTHORS: Jin Young Choi

  KEYWORDS: ESD Protection, Diode Protection Device, Bipolar Transistor, Mixed-Mode Simulation, RF IC

  JOURNAL NAME: Circuits and Systems, Vol.7 No.9, July 19, 2016

  ABSTRACT: In this work, we show that an excessive lattice heating problem can occur in the diode electrostatic discharge (ESD) protection device connected to a VDDbus in the popular diode input protection scheme, which is favorably used in CMOS RF ICs. To figure out the reason for the excessive lattice heating, we construct an equivalent circuit for input human-body model (HBM) test environment of a CMOS chip equipped with the diode protection circuit, and execute mixed-mode transient simulations utilizing a 2-D device simulator. We analyze the simulation results in detail to show out that a parasitic pnp bipolar transistor action relating nearby p+-substrate contacts is responsible for the excessive lattice heating in the diode protection device, which has never been focused before anywhere.