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Ly, D. and Chow, P. (2010) High-Performance Reconfigurable Hardware Architecture for Restricted Boltzmann Machines. IEEE Transactions on Neural Networks, 21, 1780-1792.
http://dx.doi.org/10.1109/TNN.2010.2073481

has been cited by the following article:

• TITLE: FPGA Implementation of a Scalable and Highly Parallel Architecture for Restricted Boltzmann Machines

  AUTHORS: Kodai Ueyoshi, Takao Marukame, Tetsuya Asai, Masato Motomura, Alexandre Schmid

  KEYWORDS: Deep Learning, Restricted Boltzmann Machines (RBMs), FPGA, Acceleration

  JOURNAL NAME: Circuits and Systems, Vol.7 No.9, July 8, 2016

  ABSTRACT: Restricted Boltzmann Machines (RBMs) are an effective model for machine learning; however, they require a significant amount of processing time. In this study, we propose a highly parallel, highly flexible architecture that combines small and completely parallel RBMs. This proposal addresses problems associated with calculation speed and exponential increases in circuit scale. We show that this architecture can optionally respond to the trade-offs between these two problems. Furthermore, our FPGA implementation performs at a 134 times processing speed up factor with respect to a conventional CPU.