TITLE:
CELLA: FPGA Based Candidate Execution with Low Latency Approach for Soft MIMO Detector
AUTHORS:
Erulappan Sakthivel, Kasinathan Pounraj, Veluchamy Malathi, Muruganantham Arunraja, Govindaraj Perumalvignnesh
KEYWORDS:
Multiple-Input—Multiple-Output (MIMO), Field Programmable Gate Array, Parallel Candidate Adding
JOURNAL NAME:
Circuits and Systems,
Vol.7 No.8,
June
20,
2016
ABSTRACT: This paper describes the
design and Field Programmable Gate Array (FPGA) based 4 × 4 breadth heuristic
Multiple-Input—Multiple-Output (MIMO) decoder using 16 and 64 Quadrature
Amplitude Modulation (QAM) schemes. The intention of this work is to observe
the performance of Candidate Execution with Low Latency Approach for soft MIMO
detector in FPGA (CELLA). The Smart Ordering and Candidate Adding (SOCA),
Parallel Candidate Adding (PCA) and Backward Candidate Adding (BCA) give better
performance in terms of Bit Error Rate (BER) or chip level service. In order to
attain both BER and FPGA level performance in a single system, CELLA is
developed in this work. Simulation and experimental results demonstrate the
effectiveness of the proposed work under the system 4 × 4 MIMO-OFDM employing
16 QAM and 64 QAM. The proposed experiment is implemented in Xilinx Virtex 5
C5VSX240T. The performance results, in terms of FPGA level 76% slice reduction,
58.76% throughput improvement, 75% power reduction and 87% latency reduction,
are achieved. The BER performance is observed and compared with the
conventional algorithms. Thus, the proposed work achieves better outcome than
the conventional work.