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Azimi, M., Cherukuri, N., Jayasimha, D.N., Kumar, A., Kundu, P., Park, S., Schoinas, I. and Vaidya, A.S. (2007) Integration Challenges and Tradeoffs for Tera-Scale Architectures. Intel Technology Journal, 11, No. 3.
http://dx.doi.org/10.1535/itj.1103.01

has been cited by the following article:

• TITLE: FSM Based DFS Link for Network on Chip

  AUTHORS: Erulappan Sakthivel, Veluchamy Malathi, Muruganantham Arunraja, Govinndaraj Perumalvignesh

  KEYWORDS: Network-on-Chip (NoC), Dynamic Frequency Scaling (DFS), Finite State Machines (FSM)

  JOURNAL NAME: Circuits and Systems, Vol.7 No.8, June 20, 2016

  ABSTRACT: As low power consumption is the main design issue involved in a network on chip (NoC), researchers are concentrating more on both algorithms and architectural approaches. The conventionalDynamic Frequency Scaling (DFS) and history based Frequency Scaling (HDFS) algorithms are utilized to process the energy constrained data traffic. However, these conventional algorithmsachieve higher energy efficiencies, and they result in performance degradation due to the auxiliary latency between clock domains. In this paper, we present a variable power optimization interface for NoCusing a Finite State Machine (FSM) approach to attain better performance improvement. The parameters are estimated using 45 nm TSMCCMOS technology. In comparison with DFS system, theevaluation results show that FSM-DFS link achieves 81.55% dynamic power savings on the links inthe on-chip network, and 37.5% leakage power savings of the link. Also, this proposed work isevaluated for various performance parameters and compared with conventional work. Thesimulation results are superior to conventional work.