TITLE:
Area and Speed Efficient Implementation of Symmetric FIR Digital Filter through Reduced Parallel LUT Decomposed DA Approach
AUTHORS:
S. C. Prasanna, S. P. Joy Vasantha Rani
KEYWORDS:
Distributed Arithmetic, Field Programmable Gate Array (FPGA), Finite-Impulse Response (FIR) Filter, High Speed, Reduced Look-Up Table (LUT)
JOURNAL NAME:
Circuits and Systems,
Vol.7 No.8,
June
9,
2016
ABSTRACT: This brief proposes an
area and speed efficient implementation of symmetric finite impulse response
(FIR) digital filter using reduced parallel look-up table (LUT) distributed
arithmetic (DA) based approach. The complexity lying in the realization of FIR
filter is dominated by the multiplier structure. This complexity grows further
with filter order, which results in increased area, power, and reduced speed of
operation. The speed of operation is improved over multiply-accumulate approach
using multiplier less conventional DA based design and decomposed DA based
design. Both the structure requires B clock cycles to get the filter output for
the input width of B, which limits the speed of DA structure. This limitation
is addressed using parallel LUTs, called high speed DA FIR, at the expense of
additional hardware cost. With large number of taps, the number of LUTs and its
size also becomes large. In the proposed method, by exploiting coefficient
symmetry property, the number of LUTs in the decomposed DA form is reduced by a
factor of about 2. This proposed approach is applied in high speed DA based FIR
design, to obtain area and speed efficient structure. The proposed design
offers around 40% less area and 53.98% less slice-delay product (SDP) than the
high throughput DA based structure when it’s implemented over Xilinx Virtex-5
FPGA device-XC5VSX95T-1FF1136 for 16-tap symmetric FIR filter. The proposed
design on the same FPGA device, supports up to 607 MHz input sampling
frequency, and offers 60.5% more speed and 67.71% less SDP than the systolic DA
based design.