TITLE:
A New Clock Gated Flip Flop for Pipelining Architecture
AUTHORS:
Krishnamoorthy Raja, Siddhan Saravanan
KEYWORDS:
Selective Look Ahead Clock Gating, Clock Gating, Clock Networks, Dynamic Power Reduction
JOURNAL NAME:
Circuits and Systems,
Vol.7 No.8,
June
9,
2016
ABSTRACT: The objective of the work
is to design a new clock gated based flip flop for pipelining architecture. In
computing and consumer products, the major dynamic power is consumed in the
system’s clock signal, typically about 30% to 70% of the total dynamic
(switching) power consumption. Several techniques to reduce the dynamic power
have been developed, of which clock gating is predominant. In this work, a new
methodology is applied for gating the Flip flop by which the power will be
reduced. The clock gating is employed to the pipelining stage flip flop which
is active only during valid data are arrived. The methodology used in project
named Selective Look-Ahead Clock Gating computes the clock enabling signals of
each FF one cycle ahead of time, based on the present cycle data of those FFs
on which it depends. Similarly to data-driven gating, it is capable of stopping
the majority of redundant clock pulses. In this work, the circuit implementation
of the various blocks of data driven clock gating is done and the results are
observed. The proposed work is used for pipelining stage in microprocessor and
DSP architectures. The proposed method is simulated using the quartus for
cyclone 3 kit.