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Prasath, R.A. and Kumar, P.G. (2015) A 8b 20MS/s 1.2 V Digital Ramp Asynchronous SAR ADC Using MTS Algorithm IN 0.13 nm CMOS Process. Journal of Revista Cientifica-Facultad De Ciencias Veterinarias, 25, 21-27.
http://www.cientificaonline.com/index.php/cientifica/article/view/726

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• TITLE: Design of Low Power Level Shifter Circuit with Sleep Transistor Using MultiSupply Voltage Scheme

  AUTHORS: Raveendran Arun Prasath, Parasuraman Ganesh Kumar

  KEYWORDS: Level shifter (LS), MultiSupply Voltage Design (MSVD), Subthreshold operation, Ultralow Power

  JOURNAL NAME: Circuits and Systems, Vol.7 No.7, May 30, 2016

  ABSTRACT: New low-power Level Shifter (LS) circuit is designed by using sleep transistor with Multi Threshold CMOS (MTCMOS) technique for robust logic voltage shifting from sub-threshold to above- threshold domain. MultiSupply Voltage Design (MSVD) technique is mainly used for energy and speed in modern system-on-chip. In MSVD, level shifters are required to allow different voltage supply to shift from the lower power supply voltage to the higher power supply voltage. This new low-power level shifter circuit is also used for fast response and low leakage power consumption. This low leakage power consumption can be achieved through insertion of sleep transistor and proper transistors sizing. The proposed design efficiently converts 100 mv input signal into 1 v output signal and achieves the power of 2.56 nW by using 90 nm technology.