Article citationsMore>>

Thapliyal, H. and Srinivas, M.B. (2004) High Speed Efficient N X N Bit Parallel Hierarchical Overlay Multiplier Architecture Based on Ancient Indian Vedic Mathematic. Transactions on Engineering, Computing and Technology, 2, 225-228.

has been cited by the following article:

• TITLE: Design and Implementation of Efficient Reversible Arithmetic and Logic Unit

  AUTHORS: Subramanian Saravanan, Ila Vennila, Sudha Mohanram

  KEYWORDS: Reversible Logic Gates, Reversible Logic Circuits, Reversible Multiplier Circuits, Vedic Multiplier, ALU

  JOURNAL NAME: Circuits and Systems, Vol.7 No.6, May 11, 2016

  ABSTRACT: In computing architecture, ALU plays a major role. Many promising applications are possible with ATMEGA microcontroller. ALU is a part of these microcontrollers. The performance of these microcontrollers can be improved by applying Reversible Logic and Vedic Mathematics. In this paper, an efficient reversible Arithmetic and Logic Unit with reversible Vedic Multiplier is proposed and the simulation results show its effectiveness in reducing quantum cost, number of gates, and the total number of logical calculations.