Article citationsMore>>

Agarwal, A., Hsu, S., Mathew, S., Anders, M., Kaul, H., Sheikh, F. and Krishnamurthy, R. (2011) A 128 × 128b High-Speed Wide-And Match-Line Content Addressable Memory in 32 nm CMOS. 2011 Proceedings of the IEEE ESSCIRC (ESSCIRC), Helsinki, 12-16 September 2011, 83-86.
http://dx.doi.org/10.1109/ESSCIRC.2011.6044920

has been cited by the following article:

• TITLE: Content Addressable Memory Using Automatic Charge Balancing with Self-Control Mechanism and Master-Slave Match Line Design

  AUTHORS: Dr. Deepa Jose, P. Suganya, Dr. Palanichamy Nirmal Kumar

  KEYWORDS: Content Addressable Memory (CAM), Match Line (ML), Master-Slave Match Line (MSML), Charge Balance, Translation Look-Aside Buffer (TLAB)

  JOURNAL NAME: Circuits and Systems, Vol.7 No.6, May 4, 2016

  ABSTRACT: Content Addressable Memory (CAM) is a type of memory used for high-speed search applications. Due to parallel comparison feature, the CAM memory leads to large power consumption which is caused by frequent pre-charge or discharge of match line. In this paper, CAM for automatic charge balancing with self-control mechanism is proposed to control the voltage swing of ML for reducing the power consumption of CAM. Another technique to reduce the power dissipation is to use MSML, it combines the master-slave architecture with charge minimization technique. Unlike the conventional design, only one match line (ML) is used, whereas in Master-Slave Match Line (MSML) one master ML and several slave MLs are used to reduce the power dissipation in CAM caused by match lines (MLs). Theoretically, the match line (ML) reduces the power consumption up to 50% which is independent of search and match case. The simulation results using Cadence tool of MSML show the reduced power consumption in CAM and modified CAM cell.