TITLE:
Architectural Design of 32 Bit Polar Encoder
AUTHORS:
G. Indumathi, V. P. M. B. Aarthi Alias Ananthakirupa, M. Ramesh
KEYWORDS:
Polar Encoder, Folding, Very Large Scale Integration (VLSI) Architecture, Field Programmable Gate Array (FPGA)
JOURNAL NAME:
Circuits and Systems,
Vol.7 No.5,
April
29,
2016
ABSTRACT: The rapid development in
the digital circuit design enhances the applications on very large scale
integration era. Encoders are one among the digital circuits found in all
communication systems. The polar encoding is mainly meant for its channel
achieving property. It finds its application in communications, sensing and
information theory. This coding proposed by Erdal Arikan is significant because
of its zero error floors and simple architecture for hardware implementation.
In this paper, a folded polar encoder is designed to start from the fully
parallel architecture and proceeds with its data flow graph, delay requirement
calculation, lifetime analysis and register allocation, which results in a very
large scale integration architecture with minimum hardware utilization. The
results are simulated for 4 and 8 parallel folded 32-bit polar encoder using
Xilinx 14.6 ISIM and implemented in Virtex 5 field programmable gate array. A
comparison is made on fully parallel and various folding techniques based on
their resource utilization.