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S. Malik, A. R. Wang, R. K. Brayton and A. Sangiovarmi-Vincentelli, “Logic Verification Using Binary Decision Diagrams in a Logic Synthesis Environment,” Proceedings of International Conference on Computer-Aided Design, Santa Clara, 7-10 November 1988, pp. 6-9. doi:10.1109/ICCAD.1988.122451

has been cited by the following article:

• TITLE: Algorithmic Optimization of BDDs and Performance Evaluation for Multi-level Logic Circuits with Area and Power Trade-offs

  AUTHORS: Saurabh Chaudhury, Anirban Dutta

  KEYWORDS: Algorithmic Optimization, BDDs, Genetic Algorithm, Branch & Bound, Variable Ordering, Area-Power Trade-offs

  JOURNAL NAME: Circuits and Systems, Vol.2 No.3, July 20, 2011

  ABSTRACT: Binary Decision Diagrams (BDDs) can be graphically manipulated to reduce the number of nodes and hence the area. In this context, ordering of BDDs play a major role. Most of the algorithms for input variable ordering of OBDD focus primarily on area minimization. However, suitable input variable ordering helps in minimizing the power consumption also. In this particular work, we have proposed two algorithms namely, a genetic algorithm based technique and a branch and bound algorithm to find an optimal input variable order. Of course, the node reordering is taken care of by the standard BDD package buddy-2.4. Moreover, we have evaluated the performances of the proposed algorithms by running an exhaustive search program. Experi-mental results show a substantial saving in area and power. We have also compared our techniques with other state-of-art techniques of variable ordering for OBDDs and found to give superior results.