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H. C. Osborne, “Stability Analysis if an Nth Power Phase-Locked Loop—Part II: Second- and Third-Order DPLL’s”, IEEE Transactions on Communications, Vol. 28, No. 8, 1980, pp. 1355-1364. doi:10.1109/TCOM.1980.1094772

has been cited by the following article:

• TITLE: Linearized Phase Detector Zero Crossing DPLL Performance Evaluation in Faded Mobile Channels

  AUTHORS: Qassim Nasir, Saleh Al-Araji

  KEYWORDS: Non-Uniform Sampling, Digital Phase Locked Loops, Zero Crossing DPLL, Mobile Faded Channels

  JOURNAL NAME: Circuits and Systems, Vol.2 No.3, July 6, 2011

  ABSTRACT: Zero Crossing Digital Phase Locked Loop with Arc Sine block (AS-ZCDPLL) is used to linearize the phase difference detection, and enhance the loop performance. The loop has faster acquisition, less steady state phase error, and wider locking range compared to the conventional ZCDPLL. This work presents a Zero Crossing Digital Phase Locked Loop with Arc Sine block (ZCDPLL-AS). The performance of the loop is analyzed under mobile faded channel conditions. The mobile channel is assumed to be two path fading channel corrupted by additive white Gaussian noise (AWGM). It is shown that for a constant filter gain, the frequency spread has no effect on the steady state phase error variance when the loop is subjected to a phase step. For a frequency step and under the same conditions, the effect on phase error is minimal.