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Balasubramanian, P. and John, J. (2006) Low Power Digital Design Using Modified GDI Method. The IEEE International Conference on Design and Test of Integrated Systems in Nanoscale Technology (DTIS), Tunis, 5-7 September 2006, 190-193.
http://dx.doi.org/10.1109/dtis.2006.1708713

has been cited by the following article:

• TITLE: The Design of Ultra-Low Power Adder Cell in 90 and 180 nm CMOS Technology

  AUTHORS: Masoud Sabaghi, Saeid Marjani, Abbas Majdabadi

  KEYWORDS: Adder Cell, Gate-Diffusion-Input (GDI), Bit-Serial Adder

  JOURNAL NAME: Circuits and Systems, Vol.7 No.2, February 23, 2016

  ABSTRACT: In this paper, an ultra-low power adder cell is proposed. With cascading two XNOR cells, the sum of two inputs is achieved. Regarding to advantages of m-GDI XNOR cell, we constructed the adder cell based on this architecture. The simulation results show that the power consumption of the adder cell designed with GDI technology is 12.993 μw, whereas for this cell designed with m-GDI technology is 4.1628 μw, which both are designed at 0.18 um technology. Moreover, simulation results in 90 nm CMOS technology for m-GDI adder cell show average power consumption of 0.90262 μw and 6.3222 μw in 200 MHz and 2GHz, respectively.