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Kumar, M.G.L., Khare, K. and Sharma, P. (2012) Low Voltage-Power-Area FGMOS Neural Classifier Circuit for VLSI Analog BIST. International Journal of Engineering Research & Technology, 1, 1-4.

has been cited by the following article:

• TITLE: Design of Low-Voltage, Low-Power FGMOS Based Voltage Buffer, Analog Inverter and Winner-Take-All Analog Signal Processing Circuits

  AUTHORS: Aakansha Suchitta, Richa Srivastava, Akanksha Dewaker, Maneesha Gupta

  KEYWORDS: FGMOS, Voltage Buffer, Analog Inverter, Winner-Take-All (WTA), Analog Signal Processing Circuits

  JOURNAL NAME: Circuits and Systems, Vol.7 No.1, January 13, 2016

  ABSTRACT: This paper proposes novel floating-gate MOSFET (FGMOS) based Voltage Buffer, Analog Inverter and Winner-Take-All (WTA) circuits. The proposed circuits have low power dissipation. All proposed circuits are simulated using SPICE in 180 nm CMOS technology with supply voltages of ±1.25 V. The simulation results demonstrate increase in input range for FGMOS based voltage buffer and analog inverter and maximum power dissipation of 0.5 mW, 1.9 mW and 0.429 mW for FGMOS based voltage buffer, analog inverter and WTA circuits, respectively. The proposed circuits are intended to find applications in low voltage, low power consumer electronics.