TITLE:
Design and Implement of Low Power Consumption SRAM Based on Single Port Sense Amplifier in 65 nm
AUTHORS:
Shunrui Li, Jianjun Chen, Zuocheng Xing, Jinjin Shao, Xi Peng
KEYWORDS:
Single Port Sense Amplifier, SRAM Design, Low Power Design, 8T SRAM
JOURNAL NAME:
Journal of Computer and Communications,
Vol.3 No.11,
November
19,
2015
ABSTRACT: With the rapid development of integrated
circuits [1], low power consumption has become a constant pursuiting goal of
the designer in chip design. As the memory almost takes up the area of the
chip, reducing memory power consumption will significantly reduce the overall
power consumption of the chip; according to ISSCC’s 2014 report about technology
trends discussions, there two points of the super-low power SRAM design: 1)
design a more effective static and dynamic power control circuit for each key
module of SRAM; 2) ensure that in the case of the very low VDD min, SRAM can
operating reliably and stably. This paper makes full use reliable of 8T cell, and
the single-port sense amplifier has solved problems in the traditional 8T cell
structure, making the new structure of the memory at a greater depth still
maintain good performance and lower power consumption. Compared with the
designed SRAM the SRAM generated by commercial compiler, as the performance
loss at SS corner does not exceed 10%, the whole power consumption could be
reduced by 54.2%, which can achieve a very good effect of low-power design.