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Aporntewan, C. and Chongstitvatana, P. (2001) Hardware Implementation of the Compact Genetic Algorithm. Proceedings of the 2001 IEEE Congress on Evolutionary Computation, Seoul, 27-30 May 2001, 624-629.http://dx.doi.org/10.1109/cec.2001.934449

has been cited by the following article:

• TITLE: Implementation of High Performance Electronic Circuits for Zero Suppression and Encoding of Digital Signals

  AUTHORS: Ashraf H. Yahia, Amr Radi, Salwa M. Youssef

  KEYWORDS: DAQ, FPGA, VHDL, ASICs, ISE, ISim

  JOURNAL NAME: Journal of Signal and Information Processing, Vol.6 No.3, August 25, 2015

  ABSTRACT: This paper presents a design of a data processing circuit for receiving digital signals from front end-electronic board chips of a specific nuclear detector, encoding and triggering them via specific optical links operating at a specific frequency. Such processed signals are then fed to a data acquisition system (DAQ) for analysis. Very high-speed integrated circuit hardware description language (VHDL) algorithms and codes were created to implement this design using field programmable gate array (FPGA) devices. The obtained data were simulated using international standard simulators.