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Alpman, E., Lakdawala, H., Carley, L.R. and Soumyanath, K. (2009) A 1.1 V 50 mW 2.5 GS/s 7 b Time-Interleaved C-2C SAR ADC in 45 nm LP Digital CMOS. IEEE International Solid-State Circuits Conference Digest Technical Papers, San Francisco, 8-12 Feburary 2009, 76-77.

has been cited by the following article:

• TITLE: A 0.5-V, 1.2-GS/s, 6-Bit Flash ADC Using Temporarily-Boosted Comparator

  AUTHORS: Kenichi Ohhata, Masataro Iwamoto, Naoto Yamaguchi

  KEYWORDS: ADC, Low Voltage, Flash, Comparator, Calibration

  JOURNAL NAME: Circuits and Systems, Vol.6 No.8, August 20, 2015

  ABSTRACT: A low-voltage, high-speed flash ADC is designed. The bottleneck of the operation speed in the low-voltage region is the delay time increase of the comparator. The temporarily boosted comparator is proposed to address this problem. The proposed circuit only boosts the supply voltage in the comparison phase, and therefore, can reduce the delay time while keeping the power overhead to a minimum. Moreover, the body bias control calibration is combined with the temporarily boosted technique. This helps to create a low-power and high-precision comparator. A 0.5-V, 6-bit flash ADC was designed by using 65-nm CMOS technology to demonstrate the effectiveness of the proposed technique. The simulation results showed a high sampling frequency of 1.2 GHz, a low power consumption of 1.4 mW, and an FOM of 28 fJ/conv.-step even at a low supply voltage of 0.5 V.