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Saha, P., Banerjee, A., Bhattacharyya, P. and Dandapat, A. (2011) High Speed ASIC Implementation of Complex Multiplier using VEDIC Mathematics. Proceeding of the 2011 IEEE Students’ Technology Symposium, Kharagpur, 14-16 January 2011, 237-341.

has been cited by the following article:

• TITLE: High Performance Novel Square Root Architecture Using Ancient Indian Mathematics for High Speed Signal Processing

  AUTHORS: Arindam Banerjee, Aniruddha Ghosh, Mainuck Das

  KEYWORDS: Vedic Mathematics, Bakhshali Mathematics, Duplex, Yavadunam Sutra

  JOURNAL NAME: Advances in Pure Mathematics, Vol.5 No.8, June 11, 2015

  ABSTRACT: Novel high speed energy efficient square root architecture has been reported in this paper. In this architecture, we have blended ancient Indian Vedic mathematics and Bakhshali mathematics to achieve a significant amount of accuracy in performing the square root operation. Basically, Vedic Duplex method and iterative division method reported in Bakhshali Manuscript have been utilized for that computation. The proposed technique has been compared with the well known Newton-Raphson’s (N-R) technique for square root computation. The algorithm has been implemented and tested using Modelsim simulator, and performance parameters such as the number of lookup tables, propagation delay and power consumption have been estimated using Xilinx ISE simulator. The functionality of the circuitry has been checked using Xilinx Virtex-5 FPGA board.