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Chou, T.L. and Roy, K. Statistical Estimation of Digital Circuit Activity Considering Uncertainty of Gate Delays. IEICE (Japan) Transactions on Fundamentals of Electronics, Communications and Computer Sciences, Accepted for Publication.

has been cited by the following article:

• TITLE: Design of Ultra-Low Power PMOS and NMOS for Nano Scale VLSI Circuits

  AUTHORS: Ashok Babu Ch, J. V. R. Ravindra, K. Lalkishore

  KEYWORDS: Power Delay Product, Average Power, Static Power, Delay, Dynamic Threshold CMOS

  JOURNAL NAME: Circuits and Systems, Vol.6 No.3, March 25, 2015

  ABSTRACT: CMOS devices play a major role in most of the digital design, since CMOS devices have larger density and consume less power. The integrated circuit performance mostly depends on the basic devices and its scaling methods, but in conventional CMOS devices in ultra deep submicron technology, leakage power becomes the major portion apart of dynamic power. The demerits of the conventional CMOS is less speed and, more leakage, for any digital design PDP is the figure of merit which can be used to determine energy consumed per switching event, hence we designed a NOVEL NMOS and PMOS which has superior performance than conventional PMOS and NMOS, the design and performance checked at 90 nm, 180 nm and 45 nm technology and calculate the performance values.