TITLE:
Fault Tolerance Limits and Input Stimulus Selection Using an Implemented FPGA-Based Testing System
AUTHORS:
Papakostas K. Dimitrios, Pouros P. Sotirios, Vassios D. Vassilios
KEYWORDS:
Fault Detection, External Testing System
JOURNAL NAME:
Journal of Computer and Communications,
Vol.2 No.13,
November
19,
2014
ABSTRACT: In this paper, the selection of fault
tolerance limits and input stimulus using an implemented adaptive FPGA-based
testing system based on a method utilizing wavelet transformation of the
current waveforms is presented. The testing scheme is innovative because it
offers the ability of applying different input stimulus signals with respect to
the requirements of the examined circuit. Moreover, the method used is simple,
offers a single-point test measurement solution and may easily be adapted to
test various other analog and mixed-signal systems. Experimental results are presented
showing the advantages of the proposed testing scheme.