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Boning, D. and Nassif, S. (2001) Models of Process Variations in Device and Interconnect. In Chandrakasan, A., Bowhill, W.J. and Cox, F., Eds., Design of High-Performance Microprocessor Circuits, Chapter 6, IEEE Press, 98-115.

has been cited by the following article:

• TITLE: Robust Optimization for Gate Sizing Considering Non-Gaussian Local Variations

  AUTHORS: Jin Sun Janet M. Roveda

  KEYWORDS: Robust Gate Sizing, Second Order Cone, Geometric Programming, Budget of Uncertainty, Parameter Variations

  JOURNAL NAME: Applied Mathematics, Vol.5 No.16, September 4, 2014

  ABSTRACT: This paper employs a new second-order cone (SOC) model as the uncertainty set to capture non-Gaussian local variations. Then using robust gate sizing as an example, we describe the detailed procedures of robust design with a budget of uncertainty. For a pre-selected probability level of yield protection, this robust method translates uncertainty budgeting problems into regular robust optimization problems. More importantly, under the assumption of non-Gaussian distributions, we show that within-die variations will lead to varying sizes of uncertainty sets at different nominal values. By using this new model of uncertainty estimation, the robust gate sizing problem can be formulated as a Geometric Program (GP) and therefore efficiently solved.