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(2009) IEEE Standard for Reduced-Pin and Enhanced-Functionality Test Access Port and Boundary-Scan Architecture. IEEE Std 1149.7-2009, 985.
http://dx.doi.org/10.1109/IEEESTD.2010.5412866

has been cited by the following article:

• TITLE: An IEEE 1149.x Embedded Test Coprocessor

  AUTHORS: Ukbagiorgis Iyasu Gebremeskel, José Manuel Martins Ferreira

  KEYWORDS: Built-In Test, Boundary-Scan, Embedded Coprocessors, MicroBlaze, IEEE 1149.1, IEEE 1149.7

  JOURNAL NAME: Circuits and Systems, Vol.5 No.7, July 23, 2014

  ABSTRACT: This paper describes a microprogrammed architecture for an embedded coprocessor that is able to control IEEE 1149.1 to IEEE 1149.7 test infrastructures, and explains how to expand the supported test command set. The coprocessor uses a fast simplex link (FSL) channel to interface a 32-bit MicroBlaze CPU, but it can work with any microprocessor core that accepts this simple FIFO-based interface method. The implementation cost (logic resource usage for a Xilinx Spartan-6 FPGA) and the performance data (operating frequency) are presented for a test command set comprising two parts: 1) the full IEEE 1149.1 structural test operations; 2) a subset of IEEE 1149.7 operations selected to illustrate the implementation of advanced scan formats.