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Rosales, M.D., Hizon, J.R.E., Alarcon, L.P. and Sabido, D.J. (2005) Monolithic Spiral Inductors for a 0.25 um Digital CMOS Process. Proceedings of IEEE Region 10 Conference, Melbourne, 21-24 November, 1-6.

has been cited by the following article:

• TITLE: Mitigating Time Interval Error (TIE) in High-Speed Baseband Digital Transports: Design for Delay Compensation at Baseband Infrastructure of Smart-Phones Using Fractal Dispersive Delay-Lines

  AUTHORS: Perambur S. Neelakanta, Aziz U. Noori

  KEYWORDS: Time-Interval Error, Smart-Phones, Fractal Inductors, Delay-Lines Insert

  JOURNAL NAME: Circuits and Systems, Vol.5 No.5, April 29, 2014

  ABSTRACT: A major concern in modern smart-phones and hand-held devices is a way of mitigating the time interval error (TIE) perceived at high-speed digital transits along the traces of the circuit-board (rigid and or flexible) used in baseband infrastructures. Indicated here is a way of adopting a planar fractal inductor configuration to improvise the necessary time-delay in the transits of digital signal phase jitter and reduce the TIE. This paper addresses systematic design considerations on fractal inductor geometry commensurate with practical aspects of its implementation as delaylines in the high-speed digital transports at the baseband operations of smart-phone infrastructures. Experimental results obtained from a test module are presented to illustrate the efficacy of the design and acceptable delay performance of the test structure commensurate with the digital transports of interest.