TITLE:
A 1-GHz, 7-mW, 8-Bit Subranging ADC without Resistor Ladder Using Built-In Threshold Calibration
AUTHORS:
Kenichi Ohhata, Wataru Yoshimura, Daiki Tabira, Futoshi Shimozono, Masataro Iwamoto
KEYWORDS:
Analog-to-Digital Convertor; Subranging Architecture; Resistor Ladder; Foreground Calibration; Offset Drift
JOURNAL NAME:
Circuits and Systems,
Vol.5 No.4,
March
28,
2014
ABSTRACT: A subranging
analog-to-digital converter (ADC) features high-speed and relatively low-power.
The limiting factors of power reduction in subranging ADCs are the resistor
ladder and the comparator. We propose an ADC architecture combining a
capacitive digital-to-analog convertor and built-in threshold calibration to
eliminate the resistor ladder, resulting in a low-power subranging ADC. We also
propose a calibration technique comprising of metal-oxide-metal capacitor, MOS
switch, and scaling capacitor to reduce the power consumption of the comparator
and an offset drift compensation technique to enable precise foreground
calibration. We designed an 8-bit, 1-GHz subranging ADC by applying these
techniques, and post-layout simulation results demonstrated a power consumption
of 7 mW and figure of merit of 51 fJ/conv.-step.