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J. McNeill, M. C. W. Coln and B. J. Larivee, “‘Split ADC’ Architecture for Deterministic Digital Background Cali bration of a 16Bit 1MS/s ADC,” IEEE Journal of Solid State Circuits, Vol. 40, No. 12, 2005, pp. 24372445.
http://dx.doi.org/10.1109/JSSC.2005.856291

has been cited by the following article:

• TITLE: A Domain Extension Algorithm for Digital Error Correction of Pipeline ADCs

  AUTHORS: Ting Li, Chao You

  KEYWORDS: Behavioral Simulation; Comparator Offsets; Domain Extension Algorithm; Pipeline ADCs

  JOURNAL NAME: Circuits and Systems, Vol.5 No.2, February 25, 2014

  ABSTRACT: A domain extension algorithm to correct the comparator offsets of pipeline analog-to-digital converters (ADCs) is presented, in which the 1.5-bit/stage ADC quantify domain is extended from a three-domain to a five-domain. This algorithm is designed for high speed and low comparator accuracy application. The comparator offset correction ability is improved. This new approach also promises significant improvements to the spurious-free dynamic range (SFDR), the total harmonic distortion (THD), the signal-to-noise ratio (SNR) and the minor analog and digital circuit modifications. Behavioral simulation results are presented to demonstrate the effectiveness of the algorithm, in which all absolute values of comparator offsets are set to |3Vref/8|. SFDR, THD and SNR are improved, from 34.62-dB, 34.63-dB and 30.33-dB to 60.23-dB, 61.14-dB and 59.35-dB, respectively, for a 10-bit pipeline ADC.