Article citationsMore>>

A. Shikata, R. Sekimoto, T. Kuroda and H. Ishikuro, “A 0.5 V 1.1 MS/sec 6.3 fJ/Conversion-Step SAR-ADC with Tri-Level Comparator in 40nm CMOS,” IEEE Journal of Solid-State Circuits, Vol. 47, No. 4, 2012, pp. 1022-1030. http://dx.doi.org/10.1109/JSSC.2012.2185352

has been cited by the following article:

SCIRP Newsletter
Copyright © 2006-2026 Scientific Research Publishing Inc. All Rights Reserved.
Top