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Y.-K. Cho, Y.-D. Jeon, J.-W. Nam and J.-K. Kwon, “A 9-bit 80 MS/s Successive Approximation Register Analog-to-Digital Converter with a Capacitor Reduction Technique,” IEEE Transactions on Circuits and Systems II: Express Briefs, Vol. 57, No. 7, 2010, pp. 502-506.

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